This invention relates to the field of microprogrammable digital processing systems.
As is well understood, central processing units (CPU) generally comprise an arithmetic section (ALU), a general register file, a control section, and a memory interface section. The CPU communicates with an external main memory and input/output circuits. The CPU control section retrieves instructions from the main memory and decodes then to establish the operations required and sequentially generates signals which define the data paths within the computer between the arithmetic unit, the main memory and various internal storage elements within the computer. The routing of data between the main memory machine registers and output circuitry is also carried out by such control section. Generally, specified portions of a microprogram control memory are addressed by an operation code mapping memory and subportions thereof are sequentially addressed by a microprogram sequencer source to produce sequential output instructions. A branch address source also controls the microprogram control memory to address it in a manner to cause it to jump where required to a new section therein, from where sequential operation may continue. These systems are currently familiar to those skilled in the art and a more detailed description of them may be found in U.S. Pat. No. 3,953,833 to Shapiro, dated Apr. 27, 1976 and incorporated by reference herein. For further details, reference may also be made to U.S. Pat. Nos. 3,859,636, and 3,800,293, also incorporated by reference herein. For descriptions of microprogrammed digital processors, their components and modes of operation, developed by the assignee of the present invention, see the following publications also incorporated by reference herein: "Designing the Maximum Performance into Bit-Sliced Mini Computers" by Gerald F. Muething, Jr. at page 91 through 96 of "Electronics" Magazine of September 30, 1976; a paper entitled "The Bit Sliced Bi-Polar Microprocessor. . ." written by Gerald F. Muething, Jr. and Harvey L. Siegel and presented at National Aerospace and Electronics Conference on May 19, 1977, at Dayton, Ohio.
The interconnection of a plurality of microprocessors to achieve higher performance than that which is available with a single processor is deemed highly desirable. In the past, processor intercommunication at the macro level has been accomplished with respect to data exchanged primarily through shared memory or shared input/output devices. It is deemed highly desirable to provide a network of two or more microprogrammed digital processors which eliminate the need for pre-specification of masters or slaves in linked processor networks, so that the master/slave relationship can be dynamically varied, in order to match processor resources to the data processing load. It is a further object of the invention to establish redundant processor configurations which reduce redundancy overhead and improve system availability and reliability. It is further desirable to provide processor network configurations which readily permit external observation and simulation of the control sections of the processors which is useful in testing such processors.